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UltraZED-EV Port of the ZCU106 VCU TRD

Avnet IoTConnect Demo on STM32 Boards ST - B-L475E-IOT01A (DISCO_L475VG_IOT01A) / B-L4S5I-IOT01A

Developed with Vivado 2022.1, these behavioral simulations show how to use the Video Test Pattern Generator and highlight how to control the test pattern generation framerate using a Video Timing Controller and Video In to AXI Stream conversion IP. The simulation simulations a QQVGA (160x120) resolution frame size, showing 4 frames generated as fast as the TPG can generate them at 25MHz bus clock, then shows 4 frames generated with 60fps refresh rate timine (1.944MHz Pixel Clock).

This article is a complete flow to create a Linux image using Yocto 2021.1.

This lab describes the process for customizing the Xilinx Yocto Manifest to pull the users image modifications from their personal repo.

ZCU104 DPU Example Designs for the Vivado Flow.

A demo on Cypress PSoC 6 WiFi-BT Pioneer Kit for Avnet IoTConnect mbed C/C++ SDK - http://iotconnect.io/

Scripted build examples for generating custom ZCU106 Vitis Platforms with Overlay Support, including DPU, SOFTMAX, VVAS HLS Accelerators, etc...)

Example showing how to build the platform and demo for the zcu104_vcu_ml reference design/demo

This project is a meta-user repo to demonstrate how you can add a custom layer to modify Xilinx Yocto Manifest repos without touching the actual repos themselves.

UUU (Universal Update Utility)

The example design can be used as a reference of how to properly instantiate the Video TPG in a block design and configure a Linux build to generate (and display) test patterns using GStreamer. Four test pattern generator configurations are provided:

(1) Free Running mode (2) Free Running mode with Colorspace Conversion and Scaling using the Video Processing Subsystem IP (3) Rate Controlled mode (4) Rate Controlled mode with Colorspace Conversion and Scaling using the Video Processing Subsystem IP