Explore projects
-
An example project that demonstrates how to create face detection and person detection GStreamer plugins using the Xilinx Vitis-AI-Library.
Updated -
Port of design modules from the ZCU106 v2019.2 VCU TRD to the UltraZED-EV Starter Kit
Updated -
Nguyen, Harry / aibox-facerec
Apache License 2.0Modification of XLX aibox-reid app into face recognition
Updated -
Port of design modules from the ZCU106 v2019.2 VCU TRD to the UltraZED-EV Starter Kit
Updated -
Machine learning example for the ZCU104 with FMC Quad-Camera module from Avnet
Updated -
Xilinx / Versal / AI Engine / FFTs for Fun
GNU General Public License v2.0 or laterUpdated -
Updated
-
Jason's collection of custom Vitis Platform recipes. NOTE: The platforms in this repository are for training, debug and integration. WARNING: Makefile stages have been broken up into shell scripts on the back end and MAKE dependencies have been removed. If a MAKE stage fails the build will continue, so be sure to check the console log for errors when using projects from this repository.
Updated -
This GitLab repository demonstrates the process of creating an application SDK for cross-compiling applications. The compiled applications can then be copied onto an SD card root filesystem (rootFS) for testing.
Updated -
Avnet IoTConnect Demo on STM32 Boards ST - B-L475E-IOT01A (DISCO_L475VG_IOT01A) / B-L4S5I-IOT01A
Updated -
This lab will focus on applying device tree modifications to a 2021.1 Xilinx Yocto image created with the Xilinx Yocto Manifest.
Updated -
-
The example design can be used as a reference of how to properly instantiate the Video TPG in a block design and configure a Linux build to generate (and display) test patterns using GStreamer. Four test pattern generator configurations are provided:
(1) Free Running mode (2) Free Running mode with Colorspace Conversion and Scaling using the Video Processing Subsystem IP (3) Rate Controlled mode (4) Rate Controlled mode with Colorspace Conversion and Scaling using the Video Processing Subsystem IP
Updated -
This lab will focus on applying U-Boot modifications to a 2021.1 Xilinx Yocto image created with the Xilinx Yocto Manifest.
Updated -
Scripted build examples for generating custom ZCU106 Vitis Platforms with Overlay Support, including DPU, SOFTMAX, VVAS HLS Accelerators, etc...)
Updated