Explore projects
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Ports of Xilinx TRD reference projects to the Avnet UltraZED UZ7EV SOM + IO Carrier Card
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An example project that demonstrates how to create face detection and person detection GStreamer plugins using the Xilinx Vitis-AI-Library.
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Versal Image Processing Example
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Developed with Vivado 2022.1, these behavioral simulations show how to use the Video Test Pattern Generator and highlight how to control the test pattern generation framerate using a Video Timing Controller and Video In to AXI Stream conversion IP. The simulation simulations a QQVGA (160x120) resolution frame size, showing 4 frames generated as fast as the TPG can generate them at 25MHz bus clock, then shows 4 frames generated with 60fps refresh rate timine (1.944MHz Pixel Clock).
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This lab demos the process of adding applications to a Xilinx Yocto Image.
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Utilities / Binaries / Scripts / Config files to build a rootfs for different boards
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Learn how to get started working with the YoloV3 model with Darknet53 backbone from the Model Zoo in Vitis AI 3.5, including retraining the model with the COCO 2017 training dataset.
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