Explore projects
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NXP / MPU / Layerscape / Flex-Installer
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Jason's collection of custom Vitis Platform recipes. NOTE: The platforms in this repository are for training, debug and integration. WARNING: Makefile stages have been broken up into shell scripts on the back end and MAKE dependencies have been removed. If a MAKE stage fails the build will continue, so be sure to check the console log for errors when using projects from this repository.
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This lab will focus on applying U-Boot modifications to a 2024.2 Xilinx Yocto image created with the Xilinx Yocto Manifest.
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Versal Image Processing Example
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NXP / MPU / OpenBMC_imx
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Developed with Vivado 2022.1, these behavioral simulations show how to recover native video timing from an AXI4 Video Stream and how to convert natively timed video to AXI4 Streams using catalog IP blocks including the Video Tiiming Controller, AXI4 Stream to Video Out and Video In to AXI4 Stream IP. AXI4 Stream input video is simulated using a Video Test Pattern Generator and the AXI4 Video Stream Remapper IP to show how to convert from 2 pixels per clock to 1 pixel per clock.
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