Explore projects

Developed with Vivado 2022.1, these behavioral simulations show how to use the Video Test Pattern Generator and highlight how to control the test pattern generation framerate using a Video Timing Controller and Video In to AXI Stream conversion IP. The simulation simulations a QQVGA (160x120) resolution frame size, showing 4 frames generated as fast as the TPG can generate them at 25MHz bus clock, then shows 4 frames generated with 60fps refresh rate timine (1.944MHz Pixel Clock).

Learn how to get started working with the YoloV3 model with Darknet53 backbone from the Model Zoo in Vitis AI 3.5, including retraining the model with the COCO 2017 training dataset.

This article is a complete SDT flow to create a Linux image using Yocto 2024.2.

This lab will focus on applying Linux modifications to a 2024.2 Xilinx Yocto image created with the Xilinx Yocto Manifest.

iMX BSPs (Board Support Packages)

This project is a meta-user repo to demonstrate how you can add a custom layer to modify Xilinx Yocto Manifest repos without touching the actual repos themselves.

ZCU104 DPU Example Designs for the Vivado Flow.

This lab will focus on applying U-Boot modifications to a 2024.2 Xilinx Yocto image created with the Xilinx Yocto Manifest.

UUU (Universal Update Utility)

Xilinx Petalinux GStreamer Command and Pipeline Element Reference.