Explore projects
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This lab will focus on applying U-Boot modifications to a 2024.2 Xilinx Yocto image created with the Xilinx Yocto Manifest.
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Ports of Xilinx TRD reference projects to the Avnet UltraZED UZ7EV SOM + IO Carrier Card
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Versal Image Processing Example
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The gitlab will demonstrate the process of creating a meta-user recipe to build custom R5 RPU applications.
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Learn how to get started working with the YoloV3 model with Darknet53 backbone from the Model Zoo in Vitis AI 3.5, including retraining the model with the COCO 2017 training dataset.
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